two units is that the CD2/23 has a +ve signal strength
control I/P which switches it to mono, where as the CD2/23A
has both +ve and -ve signal strength control I/Ps which do
not switch but blend the ~/ps to mono. There is not
CH1/64A. Parent equipment RC5L/10, RC5L/8, SE1L/5. DD
Decoder Unit. Card decoding serial data from Monitoring
and Information Centre clock unit, into indications
compatible with fault reporting transmitter family TM1M/1.
Power requirements 5V, 12V d.c. CH1/63. DD 1978.
30 Channel Decoder. This unit consists of a general
purpose microprocessor controlled logic unit which is
configured by appropriate software as the receiving end of
a digital signalling system. It accepts as input a 160 bit
per second serial data plus clock signal and decodes this
into 30 channels (bits) of parallel data plus, optionally,
one 50 bit per second serial signal in the standard
Automatic Fault Reporter/Monitoring and Information Centre
format. An adaptive buffer system allows a fast response
to changes in the parallel data without interruption of the
serial data output. Normally used with the CD2/12 coder.
Power Requirements +5V at
4U 57 way
sided unsupported board with PN1/29J panel.
Remote Decoder Unit. Decodes mu1tip1exed indications from
VHF Radio Control and Indication Panel PA6M/70 into logic
level suitable for driving TM1M/1 family of Fault Reporting
Transmitters. Power requirements 16/5V d.c. Diecast box
127mm x 191mm x 76mm. Parent equipment PA6M/70. DD 1978.
Alarm Decoder. This unit receives serial data from the
C04/3 Rugby-locked clock and decodes this into eight
independent alarm indications (four 'sleep' and four
'snooze' alarms). These are suitable for feeding a TM1M/1
automatic fault reporter. Intended for use at M.LC.'s.
Power requirements +5 V at 120 mA, -12 V at 20 mA. PCB
72 mm x 56 mm. DD 1978.
Decoder Unit. This unit contains nine BCD to seven segment
decoders to nine, seven segment, LED display modules. It
it used with a Timecode Decoder to form a Time Display
UN12P/17. DD 1979. DDMI 7.480(81)
8 x 4 Decoder Latch. Accepts 8-bit binary input, using the
two most significant bits to identify separate decoding
define within one of these blocks which group of sixteen
numbers from a range of sixty-four are to be decoded, and
an additional bit combined with these two defined groups of
eight from sixty-four in a second block. Each output
contains a latched peripheral driver capable of driving 24V
devices at 250mA maximum. Power requirements +5V.
CH1/64J. DD 1979.