CD030031 CD3/31
CD030032 CD3/32
CD030033 CD3M/33
CD3/33A,B
CD3MP/33
CD030034 CD3/34
CD030035 CD3/35
CD030036 CD3/36
CD030037 CD3/37
16 +16 Source Destination Decoder. Accepts 8 bit binary
input, using the two most significant bits to identify two
deparate decoding blocks within the unit. Two further bits
are used to define in each block which group of sixteen
numbers from a range of sixty-four are to be decoded. Each
output appears as a momentary closure of relay contacts.
Power requirements +5V. CH1/64J. DD 1979.
16 x 2 Decoder Latch. Accepts 8 bit parallel binary input,
using the two most significant bits to identify separate
decoding blocks within the unit. Two further bits are used
to define in each block which group of sixteen numbers from
a range of sixty-four are decoded in each block. Each
output contains a latched peripheral driver capable of
driving 24V devices at 250mA maximum. Power requirements
+5V. CH1/64J. DD 1979.
NICAM 3 Decoder. NICAM 3 equipment, decoder pair, input is
bitstream depending on demu1tip1exer, output is two high
quality audio signals, and signalling. Power requirements
250V AC. 4U BMM frame. Sub-units PS4/l0, PS2/275, C010/3,
UN26/ 49, UN26/ 42, CD3/38, UN27 /10, C09 /8. DD 1981. EDI
10440(1) AUG 82. DDHB 6.202(83).
NICAM 3 Decoder. Nicam 3 equipment, decoder pair, input is
2048kbit/s HDB3 bitstream to 'A' version, output is two
high quality audio signals. Basic version is basic
decoder pair. 'A' version also carries demu1tip1exing
cards. 'B' version as 'A' but also carries facilities for
"Hot Spare" function. Power requirements 250 V a.c. 4U
BMM frame. DD 1979.
O.B. NICAM 3 Decoder. The unit consists of a normal
CD3M/33 except in 2 respects.
1. The mains PSUs are replaced by the PS5/8
2. The individual cards are modified for O.B. conditions
Power requirements nominal 24 V dc. PN3/54. DD 1984.
Binary-BDC Decoder. Accepts 6-bit parallel binary inputs
which can be stored in two alternative latches under
control of a separate 2-bit binary input. 9 outputs of the
pair of latches are converted to give an ll-bit parallel.
BCD output and 3 outputs of the latches are used to derive
a strobe pulse to anyone of 8 outputs. Power requirements
+5V. 3U unsupported card 190mm long. DD 1979.
64 Way Binary-Decimal Decoder. Decodes 6-bit binary input
to
64
decimal
outputs.
CMOS
buffered
outputs.
Power
requirements +5V. CH1/64J. DD 1979.
Time Signal Decoder. The unit accepts lkHx tone with
interruption for the time signal pips and produces a gate
waveform to operate the GE1/16 Time Signal Generator.
Power requirements :tl2.5V d.c. 200mA approximately.
CH1/65B. DD 1980.
4 x 8 Decoder Latch. Accepts parallel 8-bit input. Uses
the two most significant bits to identify separate decoding
blocks within the unit. Two further bits are used to
define within one of these blocks which group of sixteen
numbers from a range of sixty-four are to be decoded. An
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