CD030038 CD3/38
CD030039 CD3/39
CD030040 CD3/40
CD3/40A
CD030041 CD3/41
CD030042 CD3/42
CD3/42A
addi tional bit combined with these two defined groups of
four from sixty-four in a second block. Each output
contains a latched peripheral driver capable of driving
24 V devices at 250 mA maximum. Power requirements +5 V.
4U unsupported board. DD 1980.
NICAM 3 Range Decoder. This unit accepts a received
Hamming code which it error corrects and decodes into three
separate range codes to control an expander. Power
requirements
5V.
Parent
equipment
CD3M/33.
DD
1980.
DDMI 6.373(80). DDHB 6.218(83).
Dual Timecode Decoder. The unit incorporates two separate
EBU Timecode decoders which will decode over a wide speed
range. The output from each decoder is in 4-bit parallel
form with a 4-bit input to select 1 of 16 groups of 4-bit
data. Power requirements +12 volts, -12 volts. 4U BMM
Unsupported
Card.
DD
1981.
DDMI
7.495(82).
DDHB
7.302(82)
Binary-BCD Decoder. Accepts 6-bi t parallel binary inputs
which are stored in two alternative latches under the
control of a separate 2-bit binary input. 9 outputs of the
pair of latches are converted to give an ll-bit parallel
BCD output and 3 outputs of the latches are used to derive
a strobe pulse to anyone of 8 outputs. 4U version of
CD3/34.
Power
requirements
+5V.
CH1/64J.
Parent
equipment PA6/132. DD 1981.
Binary-BCD Decoder. Accepts 6-bi t parallel binary inputs
which are stored in two alternative latches under the
control of a separate 2-bit binary input. 9 outputs of the
pair of latches are converted to give an ll-bi t parallel
BCD output and 3 outputs of the latches are used to derive
a strobe pulse to anyone of 8 outputs. 4 U version of
CD3/34.
'A' version allows two or more units to be bus sed together
so that analogue data may be decoded and displayed on one
meter.
Power
requirements
+5
V.
CH1/64J.
Parent
equipment PA6/157. Chassis extender CH1A/43. DD (2) 1985.
64-Way Cross-point Decoder. Accepts parallel 8-bit binary
inputs and uses the two most significant bits to identify
two separate decoding blocks within the unit. The next two
significant bits determine groups of sixteen numbers within
a range of 64 binary inputs. Linking arrangements allow a
selection from 16 decoded outputs of the 1st block and 32
outputs of the 2nd block to operate a 64-way matrix cross-
point output drive in a varied pattern. Power requirements
+5V. CH1/64J. DD 1981. DDMI 2.469(83).
Indication Decoder. Decodes BCD inputs (normally from
thumbwheel switches) to 8-bit parallel binary code and
compares this code with another similar input. A true
comparison causes this second input and a further set of 8-
bit parallel binary code to be held in latches for use
elsewhere, such as in display devices. Power requirements
+5V. CH1/64J. DD 1981. DDMI 2.470(83).
Indication Decoder. Decodes BCD inputs (normally from
thumbwheel switches) to 8-bit parallel binary code and
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