CD0300S1 CD3S/S1
CD0300S2 CD3/S2
CD0300S3 CD3M/S3
CD0300S4 CD3SM/S4
CD0300S6 CD3/S6
and presents the time information in a form that can be
handled by the UN26S/71 Microcomputer. It forms part of
the Record Bank installation at Television Centre. Power
requirements +12 V, -12 V, +S V. 4 U unsupported printed
CH4/S. DD(7) 1985. DDMI 7.S37(86).
728 kbi t/ s Decoder. The decoder converts a 728 kbit/ s
serial data stream as specified in "Draft Specification of
Standards for UK Stereo with Television Transmissions"
(Rev.3) into two 14-bit parallel PCM sound channels.
4U-PN1/29J & Unsupported Card. RD 1986.
Co-ord. Decoder. Operating on the Digital Audio Multiphase
Bus D.D.T.M. 3.291(84), this unit re-assembles the two
streams of 48 kHz x 4 'Auxiliary' bits in the AES/EBU
serial digital audio signal into two 16 kHz - sampled 12-
bit quantised 'Co-ordination' channels. Power Requirements
S V. BBC Chassis Code 4U BMM unsupported card with 'J'
width front panel. Chassis extender CH4/S. DD(3) 1986.
Analogue Output Co-ord Separator. The input to this unit
is an EBU - Serial - Digital stereo programme signal that
also carries Co-ord channel information in its auxiliary
data bits. The unit provides separate analogue Co-ord and
Chassis Code PN3/S4. Sub-units: PS4/18A, PS3/67, C010S/12,
CD3/S2, 2 x C09/9, FL4/81, FL4/83. DD(3) 1986.
D.S.S.T.TV 728kbit/sec Decoder. This decoder is designed
to receive 728kbit/sec Clock and serial Data signals from
the DSSTTV Demodulator, and convert them to two analogue
sound signals. The Decoder conforms to the stereo coding
option of Revision 4 of the UK Specification for DSSTTV.
The unit decodes, demultiplexes and expands the serial
digital data, to generate 14-bit digital sound samples on
both channels at 32kHz rate. These undergo digital-to-
analogue conversion to regenerate the original analogue
waveforms, and are de-emphasised and filtered ready for
outputting to audio amplifiers, etc. Power requirements
240Vac. PN3/S4. Sub-units PS4/44, PS2/27S, CD3S/S1,
C09S/12, FL4/86, GE2S/18. RD 1987.
Clock Recovery/QPSK Decoder. This unit forms part of the
Digital Stereo Sound with Terrestrial Television
Demodulator. The unit receives differential-encoded
symbol-rate (2 x 728kbit/sec) demodulated data, recovered
by the QPSK Demodulator unit (DM4/9) from the I & Q phase-
axes of the digital QSPK signal. The unit differentially
decodes the I & Q channel symbol-rate data, to regenerate
the 728kbit/sec serial bit-stream (TTL level) signals. The
clock recovery circuitry uses a 'Modified Mengali Tracker'
circuit, to recover a bit-rate clock (728kHz) from the
demodulated data signal. Power requirements +12V (16SmA),
-12V (70mA). CH1/64A. Chassis extender CH1A/43. Parent
equipment DM4M/8. RD 1987.
2048kbit/sec TFM Decoder. This unit accepts two quadrature
baseband signals from a DM4/10 demodulator, and provides