C008001S C08/1S
C0080016 C08/16
C0080017 C08/17
C0080018 C08/18
C0080S03 C08/S03
C0080S04 C08/S04
C0080S0S C08/S0S
L.S.I. NICAM NRZ/HDB3 Interface.
Inputs:
1) 676 kb/s NRZ data and clock (T.T.L.) or
2) 676 kb/s HDB3, 4.7 V or SOO mV p-p amplitude.
Outputs:
1) 676 kb/s NRZ data and clock; from input 1) or transcode
from input 2).
2) HDB3 transcoded from input 1) logic se1ectable to be
400 mV or 4.7 V p-p amplitude. Power requirements
+18 V, 130 mA; +S V, 70 mA; -18 V, 100 mA.
Manufactured by Pye T.V.T. Ltd.
DD 1984.
Analogue to Digital Converter. This unit converts audio at
zero programme level to an 8-bit A-law coded digital form,
sampled at 8 kHz. Bandwidth is restricted to 3.4 kHz.
Input is balanced via a front panel PO 316 jack socket.
Also has the facility to play back the encoded audio via
another PO 316 jack socket for headphone monitoring. Used
in the RD1SM/2
(SATIRE).
Requires two handshake lines.
Power requirements S V at 2S0 mA; :!:IS V at 100 mA; 3U
unsupported wirewrap card with 'A'-width Front Panel
(CH1/84). Parent equipment RD1SM/2. DD 1985.
Audio Analogue to Digital Converter. This unit forms part
of the Digital Stereo Sound with Terrestrial Television
Coder, but can also be used in other applications; for such
use, the output code can be binary, 2's complement or sign-
magni tude,
selec table
by
internal
swi tches.
Power
requirements +SV, t1SV. 4U unsupported p.c.b with PN1/29J
front panel. Chassis extender CH4/ S. Parent equipment
CD2SM/39. RD 1987.
Electra-Sony Analogue to Digital Converter. This unit
accepts the analogue shuttle/slow and TSO control voltages
from the RD4/S09 (ELECTRA) editing system, and produces an
equivalent digital 8-bit word for each analogue value.
Power requirements +SV, t12V. 4U unsupported pcb. Chassis
extender CH4/S. Parent equipment C011P/7. D&ED (C) 1987.
Converter, provides adjustable 'out of limits' trigger
pulse and 3.S digit B.C.D. from an input up to 2 OOV d.c.
For use with RDS/S01. CH1/64A chassis. DD 1977.
Video Analogue to Digital Converter. A rack mounted
version of the C08/S01 including a vent above the C 08/S01
to allow equipment heated air to escape at the rear and air
to enter to cool equipment mounted above. DD 1978.
8 Bit High Speed Video ADC. Inputs: (1) Video IV p-p high
impedance; (2) Mixed sync 2V p-p t6dB high impedance; (3)
Clock TTL balanced or unbalanced 2-20MHz. Outputs: (1)
8bit parallel NR2 (true or inverted) or offset 2's
complement (true or inverted); (2) Clock. This unit has an
input clamp and the clamp pulses may be derived from the
incoming video via an on board sync separator on an
external feed of mixed syncs. Power requirements +lSV
+0.7SV, -3v at 90mA; -lSV -0.7SV, +3V at 4S0mA; +SV to.2SV
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