COll0004 COll/4
COll0005 COll/5
COll0006 COllS/6
COll0007 COllP/7
COll0008 COllS/8
COll050l COlI/SOl
COll0502 COll/502
bits are added to each 8-bit word. A built-in clock
generator runs at 50 baud and the state of all 16 inputs is
transmitted to 40-bits. To allow error detection,
redundancy
is
added.
Power
requirements
+5V.
4U
unsupported PCB with PNl/29J front panel assembly. Parent
equipment TMlM/4. DD 1982.
MX80 Parallel to Serial Converter. To correct parallel
data from local crate bus to serial format to record on
MX80 digital tape recorder. Also contains phase locked
loop to synchronise recorder to digital crate. Power
requirements 5 V at 2 A. 4U unsupported card. Parent
equipment CD4M/13. DD 1983.
EBU Parallel to Serial Converter. Converts and formats
parallel data from local data bus to EBU "Biphase Mark"
serial code. (Phase locked to the COlO/9) Stereo system
transmits two channels A & B. Power requirements 5 V at
<1. 5 A. 4U unsupported card. Parent equipment CD4M/13.
DD 1983.
EBU Parallel to Serial Converter. This card converts
parallel data from the multiphase digital audio bus to
serial EBU data. The card accepts any two channels from
the 64 phase bus. Power requirements 5 V, 2 A max. 4 U
unsupported card. Chassis extender CHlA/43. DD(3) 1985.
DDHB 3.334(86).
Electra-Sony Parallel to Serial Converter. This unit
converts the incoming parallel commands from the RD4/509
(ELECTRA) editing system into serial commands, in
accordance with the Sony serial protocol. It also reads
all relevant serial VCR tallies, and converts them into
parallel form for returning to the editing system. Power
requirements 240V ac. CS2/23B. Sub-units PS2/l84, C08/l8,
UN26S/7l. D&ED (C) 1987.
NICAM-EBU Output Unit. This unit generates a serial output
of linear PCM from a NICAM decoder, CD3M/33. The output is
to the AES/EBU standard for serial digital audio, with a
32kHz sample rate. Power requirements +5V. 4U unsupported
pcb. Parent equipment CD3M/33. Chassis extender CH4/5.
D&ED 1987.
Parallel-to-Serial Converter. This board receives data in
8-bit words at l2MHz through two 8-bit data buses, under
the control of a separate control bus. This data is stored
in a Read/Write memory until required by the output stage.
Data leaves the board in a single serial stream at l5MHz.
The order of the bits being determined by a separate
control bus so that any bit of an 8-bit word can be sent at
anyone time. Line Synchronisation Words, Line Addresses
and Error Protection Information are also generated and
added to the serial stream as required. Power requirements
1.2A at 5V. 4U BMM unsupported card. Parent equipment
PAlM/S80. RD 1981.
280MBit/s Multiplexer. Accepts two 8-bit parallel data
feeds from vide A-D converters and generates a 280Mbit/s
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