allow a signal similar to that on the incoming circuit to
be generated and sent to line providing an acknowledgement
at
the
remote
terminal
of
the matrix
operation.
Power
requirements
::t9V
d. c.
unregulated.
PN3/23.
Sub
units
CD3/10, DM3/8, FL2/1s, MD3/12, PS2/189, SC1/2, SC1/4,
SC1/6, UN1A/S, UN12/2, UN23/38, UN23/39, UN23/40.
Supersedes EP1sM/7. DD 1978. DDHB 2.438(78).
SEOS0007 SEs/7
Data Switch Unit. The unit is a 32 bit two way changeover
switch - two inputs, one output. S to l2V CMOS levels in
and out. It is intended for switching timecode times (26
bit and sign) or user bits (32 bit). Power requirements
+SV
to
+12V
~lmA.
4U
BMM
unsupported
card.
Parent
equipment RD4L/s07. DD 1978. DDMI7.424(79).
SEOs0008 SES/8
Processor Input Switch. Accepts up to 64 digital inputs
and selects one block of 8 bits at the output. Used with a
Microprocessor card which controls the 8 bit selection.
Power requirements +sV ...lOmA.
4U BMM unsupported card.
Used in EP10/S01 and EP10/s02. DD 1980. DDMI 7.4S9(81).
SEOS0009 SES/9
Remote Switching Timer/Controller. Provides 4 independent
swi tching outputs which can be programmed over a weekly
cycle to energise and de-energise remote facilities at up
to 18 daily or weekly set times. Each switching output has
an associated alarm circuit which operates 10 minutes
before switch-off times and a lamp drive circuit which
provides a continuing indication that an alarm has been
cancelled or overridden. Programming is accomplished via
an integral keypad and there are comprehensive displays of
time of day, day of week and switching states. Based on
the Texas TMS 1122 timer, the prototype unit was developed
for standby/normal switching of camera channel CCUs. Power
requirements
240V AC mains.
CH1/64B.
Open University
1981.
SEOs0010 SES/10
Talkback Switch Unit. Provides switching of six talkback
outputs with a Latching/Non-latching selection being
available. Power requirements ::t7.sv 20mA. 3U x 7". SCPD
1981.
SEOsOOll SEs/ll
Display Interface. The unit comprises multiplexers for
address and data lines between 280 IJ.P and Display RAM,
Display Driver Counter, and 4 byte FIFO, to achieve a
'G1itch Free' display of Ram contents with full IJ.P access.
It is used in conjunction with modified UN12/10. GE7 /5,
and GE8/3. Power requirements +sV DC at lA. CH1/64J
(Unsupported 4U card). Parent equipment UN12M/s13. DD
1981.
SEOs0012 SE5/12
Data Switching Unit. The unit is designed to be used with
a C04/14 data interleaver, to bypass the unit in event of
failure. Additionally, signal processing is available for
inputs 2, 3 and 4 of the inter1eaver. Power requirements
SV DC at 100mA. 3D unsupported 1/2 card with double sided
21-way edge connector. Parent equipment TM1M/1A, 1B, 1C,
10, lE, IF. DD 1981. ODHB 2.488(83).
271

71