UN230684 UN23/684
UN23068S UN23/68S
UN230686 UN23/686
UN230687 UN23/687
UN230688 UN23/688
UN230689 UN23/689
UN230690 UN23/690
overrides the write inhibit capability. Power requirements
+S V, -S V. CH1/79. Parent equipment C06/S11. DD 1981.
Digital Field Store Output Control. Generates TTL
waveforms for the Control of Y and UV digital field stores
in the C06/Sll Transcoder. Balanced clock is fed in and
buffered to form the read clocks to the stores, the other
store signals generated are ROW/ COLUMN B ADDRESS, MIXED
BLANKING, READ ENABLE, WRITE and SELECT ADDRESS B, LOAD,
RAS and CAS. A UV identification signal is generated and
used to demu1tip1ex the UV data signal. Power requirements
+SV, -SV. CH1/79. Parent equipment C06/S11. DD 1981.
Clock Regenerator Logic Unit. This unit accepts a
teleprinter data input at levels up to 80-0-80V PP and
converts this to a TTL level data output. A sync clock is
also generated. This is TTL square timed such that the
edge occurs midway along the data bit line. Baud rate is
110. Power requirements +SV -SV or -12V. PN1/29J Front
Panel Assembly. BMM 4U Unsupported board. DD 1981.
DMA Control Unit. Controls the transfer of symbol data
from the CPU memory into the scratch pad. It is given the
address of a look-up table by the CPU and uses this to
access all data for a particular symbol by DMA, on a 1ine-
by-line basis. Power requirements SV. CH1/79. Parent
equipment EPSM/S17. DD 1982.
Timing Control Unit. Synchronises EAGLE's digital
processing to TV standard pulses. Provides correctly timed
intercept pulses to the CPU, and controls the DMA
operation. Times the DAC for a synchronous and correctly
blanked output. Power requirements SV. CH1/79. Parent
equipment EPSM/S17. DD 1982.
Interface and Control Unit. The card interfaces and
controls the other five cards in the filter section of the
68 Mbit/s digital transmission system. It configures
itself to operate in either pre or post-filter modes.
Power requirements +SV d.c. at approx. 2.3A. 4U J width,
unsupported card, with S7-way double-sided edge connector.
Parent
equipment
C09M/S08
&
C08M/S10.
DD
1982.
DDHB
1.169(82).
Suppression Control Unit. Generates the control signals
required to drive the FIS Combiner and Data Suppressor
UN26/S84. Requires an 8-bit parallel input of digital
video at 4 times colour subcarrier clock rate. Power
requirements +SV. 4U 'J' width front panel, single PCB.
Parent equipment C09M/S08. DD 1982.
Caption Generator Timer Unit. This unit has three
independant timers. Each timer can be started or stopped
locally or remotely. By counting sync pulses each timer
counts down from 9 to zero in 1 minute steps. The numeral
to be generated is sent to the relevant control card
UN23/158. Power requirements +5V. 4U unsupported card.
Parent equipment GE8M/S08. DD 1982.
329

29