UN260093 UN26/93
UN260094 UN26/94
UN26/94A
UN26009S UN26/9S
UN260096 UN26/96
UN260097 UN26/97
UN260098 UN26/98
+S v supply. Power requirements:
card 280 mm deep. D & ED 1986.
3 U unsupported Euro-
Tristran Interface. Buffers the Zeus bus of several
C010S/11 (Tristran) units to enable them to be connected to
a DEC Micro/PDP11 computer. Power requirements S V. BBC
chassis 4 U unsupported pcb with PN1/29J front panel.
Chassis extender CH4/S. Parent equipment C04SM/31.
D & ED (C) 1986.
Clock Buffer Unit. Buffer for use with Radio Data.
Buffers and splits the output of a 60 kHz Standard
Frequency Receiver (RC1/23) to give eight TTL compatible
outputs.
Power requirements +12 V d.c.
Termination
Panel PA20/49. Chassis CH1/6SA. Chassis extender CH1A/45.
TCPD 1986.
Clock Buffer Unit. As UN26/94 but front panel modified to
exclude 2 fixing holes. Power requirements +12Vdc.
Chassis code CH1/6SA. Chassis extender CH1A/ 45. TCPD
1987.
Error Feedback Unit. This unit forms part of the Digital
Vision Mixer system. It converts the 12-bit internal
standard to 9 bits using error feedbacks, on both luminance
and chrominance. Power requirements +SV. 6U Eurocard,
280mm deep. Dedicated termination panel PA20/S2. D&ED (V)
1987.
This unit forms part of the Digital Stereo Sound with
Terrestrial Television Coder. The output buffer takes
728kbit/sec data and clock signals from the coder processor
board at TTL levels, and outputs them at a signal level of
1.0V peak-to-peak into 7SQ. The data and clock signals are
available via BNC sockets on the front panel, for sending
to other equipment (eg. Modulator Unit MD4S/7).
These
signals are also available via monitor points located on
the
front
panel.
Power
requirements +SV,
+12V.
4U
unsupported p.c.b with PN1/29J front panel. Chassis
extender CH4/S. Parent equipment CD2SM/39. RD 1987.
Error Checker Unit. This is an optional unit designed for
use with the Digital Stereo Sound with Terrestrial
Television Demodulator equipment. The unit does not work
on programme; instead, it requires a fixed, pseudo-random-
binary sequence to be transmitted on the digital stereo
signal. The error checker takes clock and data from the
demodulator, and checks for bit-errors in the received data
sequence. It outputs an error pulse for each incorrect
bit. These pulses and data-clock can be used to drive a
frequency-counter which will display the bit-error-ration.
The error checker uses a self-synchronising descrambler and
resetting circuit, allowing error rates of up to 100% to be
displayed.
Power
requirements
+12V
(SOmA).
CH1/64A.
Parent equipment DM4M/8. Chassis extender CH1A/ 43. RD
1987.
Events Output Unit. This forms part of the VANTAGE Edit
Controller PA1M!S89. Its function is to provide an
interface to the Events Controller, so that up to 30
342

42