UN260581 UN26/581
UN260582 UN26/582
UN260583 UN26/583
UN260584 UN26/584
the HOB3 output stage contained in associated unit GE2/643B
which contains a phase-locked loop to derive the 676 kbit/s
clock. All inputs and outputs have TTL levels. The unit
is complementary to unit UN26/575, and forms part of 68
Mbit/s demultiplexing equipment CD4M/505. Power require-
ments +5V, at current to be advised. 4U solderwrap card
with J width front panel. Parent equipment CD4M/505. RD
1982.
Radio De-tributary Unit. The unit demultiplexes a 8448
kbit/s signal (normally containing 2 digital sound signals
for television) from a 68 Mbit/s signal. The latter is
accepted in 6-bit parallel form (at 11.456 Mword/s)
together with frame-marker pulse and a 11.456MHz clock.
The appropriate words are written into a buffer store and
the data are output at a steady rate in suitable format for
the HDB3 output stage contained in associated unit
GE2/643C, which also contains a phase-locked loop to derive
the 8448 kbit/s clock. All inputs and outputs have TTL
levels. The unit is complementary to unit UN26/577, and
forms part of 68 Mbit/s demultiplexing CD4M/505. Power
requirements +5V, at current to be advised. 4U solderwrap
card with J width front panel. Parent equipment CD4M/505.
RD 1982.
Auxiliary De-tributary Unit. The unit demultiplexes a 2048
kbit/s signal (normally containing 2 digital sound signals
for television)
from a 68 Mbit/s
signal.
The latter is
accepted in 6-bit parallel form (at 11.456 Mword/s)
together with frame-marker pulse and a 11.456MHz clock.
The appropriate words are written into a buffer store and
the data are output at a steady rate in suitable format for
the HDB3 output stage contained in associated unit GE2/643D
which also contains a phase-locked loop to derive the 2048
kbit/s clock. All inputs and outputs have TTL levels. The
unitis complementary to unit UN26/576, and forms part of 68
Mbit/s demultiplexing equipment CD4M/505. Power require-
ments +5V,
at current
to be advised.
4U solderwrap card
with J width front panel. Parent equipment CD4M/505. RD
1982.
Digital Processor Unit. The unit scrambles or descrambles
a 68 Mbit/s multip1exed signal, input and output are in the
form of 6-bi t words, with 11.456 MHz clock and a frame-
marker pulse, all at TTL levels. The unit is an optional
part of 68 Mbit/s multiplexing equipment, units CD4M/505
respectively. Power requirements +5 V at current to be
advised. 4u solderwrap card with J width front panel.
Parent equipment CD4M/504, CD4M/505. RD 1982.
FIS Combiner and Data Suppressor. Combines incoming
digital video and field interval signals (FIS) to produce a
single digital video output. The unit can also provide
field blanking by switching to an internally generated
blanking level. Control signals from Suppression Control
Unit UN23/689 are required to drive this equipment. Power
requirements +5V. 4U 'J' width front panel, single PCB.
Parent equipment C09M/508. DD 1982.
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