UN270005 UN27/5
UN270006 UN27/6
UN270007 UN27/7
UN270008 UN27/8
UN270009 UN27/9
UN270010 UN27/10
UN27/10A.B
UN2700ll UN27/ll
UN270012 UN27/12
Cursor Store. Store holding current position of cursor in
Monitoring and Information Centre remote VDU. Power
requirements 5V d.c. CH1/64J. Parent equipment UN12/6.
DD 1978.
Buffer Store Unit. First in. first out. store for use in
Monitoring and Information Centre remote VDU. Power
requirements 5V d.c. CH1/64J. Parent equipment UN12M/6.
DD 1978.
8k Byte R.A.M. Store. General purpose store for 8k by 8
bit words using static RAM's. 16 bit addressing. address
and data lines fully buffered. Power requirements +5V.
1.5A typical. CH1/64J - 57 way edge connector. DD 1978.
DDHB 2.459(82).
Store Unit. This unit stores 256. 32 bit words and is
intended for the storage of timecode times or user bits.
It has a built in rechargeable battery on the card to
maintain the supply tothe store when the equipment in which
it
is
used
is
switched
off.
12V
CMOS
levels
in
and out .
Power requirements +12V at 10mA d.c. 4U BMM unsupported
card. Parent equipment RD4/507. DD 1978. DDMI 7.428(80).
16 Page Store Unit. This unit carries eight 2K byte memory
IC's and selector IC. It provides 16 pages 0 f pre-
programmed teletext display for electronic selection of
message referring to the status of the data channels of the
13 channel PCM system. Power requirements +9V at 300mA.
CDX 3U 'J' size card (C06). Parent equipment MN8H/1. DD
1978.
Store and Sequencer. This unit contains read only memories
which control the sequence of operations in NICAM 3 coders
and decoders. and random access memories for the storage of
data awaiting processing. Power requirements 5V 610mA.
CH1/64J. Ferranti 57-way connector. Parent equipment
CD2M/17. CD3M/33. CD2M/23. DD 1981. DDHB 6.210(83).
Store and Sequencer Unit. This unit contains read only
memories which control the sequence of operations in NICAM
3 coders and decoders. and random access memories for the
storage of data awaiting processing. Power requirements
5V.
610mA.
CH1/64J.
Ferranti
57-way connector.
Parent
equipment
CD2M/17(UN27/10A)
and
CD3M/33
(UN27/10B).
DD
1980. DDMI 6.366(80).
Processor Output Latch Unit. Has 64 latched outputs which
are ddved by an 8 bit data input and 8 output select
lines. Used with a microprocessor card which controls the
unit. Power requirements +5V <lOmA. 4U un suqported card.
Used in EPIOM/501 and EPIOM/502. DD 1980. DDMI 7.460(81).
8K RAM Store. An 8K byte Static Ram Store utilising CMOS
storage components to minimise power requirements.
Separate data input and data output terminals are provided
which are commoned when connected to the standa rd Designs
Department bus. A separate power supply pin is provided
for the memory elements and power supply failure monitoring
ensures isolation of these if either the control power or
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